Datasheet

the processors never stall on these accesses. However, like all SRAM on RP2040, these banks have single-cycle access
from all masters providing no other masters are accessing the bank in the same cycle, so it is reasonable to treat
memory as a single 264kB device.
The four 64kB banks are also available at a non-striped mirror. The four 64kB regions starting at 0x21000000, 0x21010000,
0x21020000, 0x21030000 are each mapped directly to one of the four 64kB SRAM banks. Software can explicitly allocate
data and code across the physical memory banks, for improved memory performance in exceptionally demanding
cases. This is often unnecessary, as memory striping usually provides sufficient parallelism with less software
complexity.
The non-striped mirror starts at an offset of +16MB above the base of SRAM, as this is the maximum offset that allows
ARMv6M subroutine calls between the smaller banks and the non-striped larger banks.
2.6.2.1. Other On-chip Memory
Besides the 264kB main memory, there are two other dedicated RAM blocks that may be used in some circumstances:
•
If flash XIP caching is disabled, the cache becomes available as a 16kB memory starting at 0x15000000
•
If the USB is not used, the USB data DPRAM can be used as a 4kB memory starting at 0x50100000
This gives a total of 284kB of on-chip SRAM. There are no restrictions on how these memories are used, e.g. it is
possible to execute code from the USB data RAM if you choose.
2.6.3. Flash
External Flash is accessed via the QSPI interface using the execute-in-place (XIP) hardware. This allows an external
flash memory to be addressed and accessed by the system as though it were internal memory. Bus reads to a 16MB
memory window starting at 0x10000000 are translated into a serial flash transfer, and the result is returned to the master
that initiated the read. This process is transparent to the master, so a processor can execute code from the external
flash without first copying the code to internal memory, hence "execute in place". An internal cache remembers the
contents of recently-accessed flash locations, which accelerates the average bandwidth and latency of the interface.
Once correctly configured by RP2040’s bootrom and the flash second stage, the XIP hardware is largely transparent,
and software can treat flash as a large read-only memory. However, it does provide a number of additional features to
serve more demanding software use cases.
RP2040 Datasheet
2.6. Memory 149