Datasheet

Bits Name Description Type Reset
0 EN When 1, enable the cache. When the cache is disabled, all
XIP accesses
will go straight to the flash, without querying the cache.
When enabled,
cacheable XIP accesses will query the cache, and the
flash will
not be accessed if the tag matches and the valid bit is set.
If the cache is enabled, cache-as-SRAM accesses have no
effect on the
cache data RAM, and will produce a bus error response.
RW 0x1
XIP: FLUSH Register
Offset: 0x04
Description
Cache Flush control
Table 167. FLUSH
Register
Bits Description Type Reset
31:1 Reserved. - -
0 Write 1 to flush the cache. This clears the tag memory, but
the data memory retains its contents. (This means cache-as-SRAM
contents is not affected by flush or reset.)
Reading will hold the bus (stall the processor) until the flush
completes. Alternatively STAT can be polled until completion.
SC 0x0
XIP: STAT Register
Offset: 0x08
Description
Cache Status
Table 168. STAT
Register
Bits Name Description Type Reset
31:3 Reserved. - - -
2 FIFO_FULL When 1, indicates the XIP streaming FIFO is completely
full.
The streaming FIFO is 2 entries deep, so the full and
empty
flag allow its level to be ascertained.
RO 0x0
1 FIFO_EMPTY When 1, indicates the XIP streaming FIFO is completely
empty.
RO 0x1
0 FLUSH_READY Reads as 0 while a cache flush is in progress, and 1
otherwise.
The cache is flushed whenever the XIP block is reset, and
also
when requested via the FLUSH register.
RO 0x0
XIP: CTR_HIT Register
Offset: 0x0c
RP2040 Datasheet
2.6. Memory 154