Datasheet

Table 172.
STREAM_CTR Register
Bits Description Type Reset
31:22 Reserved. - -
21:0 Write a nonzero value to start a streaming read. This will then
progress in the background, using flash idle cycles to transfer
a linear data block from flash to the streaming FIFO.
Decrements automatically (1 at a time) as the stream
progresses, and halts on reaching 0.
Write 0 to halt an in-progress stream, and discard any in-flight
read, so that a new stream can immediately be started (after
draining the FIFO and reinitialising STREAM_ADDR)
RW 0x000000
XIP: STREAM_FIFO Register
Offset: 0x1c
Description
FIFO stream data
Table 173.
STREAM_FIFO
Register
Bits Description Type Reset
31:0 Streamed data is buffered here, for retrieval by the system DMA.
This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
the DMA to bus stalls caused by other XIP traffic.
RF 0x00000000
2.7. Boot Sequence
Several components of the RP2040 work together to get to a point where the processors are out of reset and able to run
the bootrom (Section 2.8). The bootrom is software that is built into the chip, performing the "processor controlled" part
of the boot sequence. We will refer to the steps before the processor is running as the "hardware controlled" boot
sequence.
The hardware controlled boot sequence is as follows:
•
Power is applied to the chip and the RUN pin is high. (If RUN is low then the chip will be held in reset.)
•
The On-Chip Voltage Regulator (Section 2.10) waits until the digital core supply (DVDD) is stable
•
The Power-On State Machine (Section 2.13) is started. To summarise the sequence:
◦
The Ring Oscillator (Section 2.17) is started, providing a clock source to the clock generators. clk_sys and
clk_ref are now running at a relatively low frequency (typically 6.5MHz).
◦
The reset controller (Section 2.14), the execute-in-place hardware (Section 2.6.3), memories (Section 2.6.2
and Section 2.6.1), Bus Fabric (Section 2.1), and Processor Subsystem (Section 2.3) are taken out of reset.
◦
Processor core 0 and core 1 begin to execute the bootrom (Section 2.8).
2.8. Bootrom
The Bootrom size is limited to 16 kB. It contains:
•
Processor core 0 initial boot sequence.
•
Processor core 1 low power wait and launch protocol.
•
USB MSC class-compliant bootloader with UF2 support for downloading code/data to FLASH or RAM.
RP2040 Datasheet
2.7. Boot Sequence 156