Datasheet

Chapter 2. System Description
This chapter describes the RP2040 key system features including processor, memory, how blocks are connected,
clocks, resets, power, and IO. Refer to Figure 2 for an overview diagram.
2.1. Bus Fabric
The RP2040 bus fabric routes addresses and data across the chip.
Figure 4 shows the high-level structure of the bus fabric. The main AHB-Lite crossbar routes addresses and data
between its 4 upstream ports and 10 downstream ports: up to four bus transfers can take place each cycle. All data
paths are 32 bits wide. Memory devices have dedicated ports on the main crossbar, to satisfy their high bandwidth
requirements. High-bandwidth AHB-Lite peripherals have a shared port on the crossbar, and an APB bridge provides bus
access to system control registers and lower-bandwidth peripherals.
Figure 4. RP2040 bus
fabric overview.
The bus fabric connects 4 AHB-Lite masters, i.e. devices which generate addresses:
•
Processor core 0
•
Processor core 1
•
DMA controller Read port
•
DMA controller Write port
These are routed through to 10 downstream ports on the main crossbar:
•
ROM
•
Flash XIP
•
SRAM 0 to 5 (one port each)
•
Fast AHB-Lite peripherals: PIO0, PIO1, USB, DMA control registers, XIP aux (one shared port)
•
Bridge to all APB peripherals, and system control registers
The four bus masters can access any four different crossbar ports simultaneously, the bus fabric does not add wait
states to any AHB-Lite slave access. So at a system clock of 125 MHz the maximum sustained bus bandwidth is 2.0
RP2040 Datasheet
2.1. Bus Fabric 15