Datasheet

GB/s. The system address map has been arranged to make this parallel bandwidth available to as many software use
cases as possible — for example, the striped SRAM alias (Section 2.6.2) scatters main memory accesses across four
crossbar ports (SRAM0…3), so that more memory accesses can proceed in parallel.
2.1.1. AHB-Lite Crossbar
At the centre of the RP2040 bus fabric is a 4:10 fully-connected crossbar. Its 4 upstream ports are connected to the 4
system bus masters, and the 10 downstream ports connect to the highest-bandwidth AHB-Lite slaves (namely the
memory interfaces) and to lower layers of the fabric. Figure 5 shows the structure of a 2:3 AHB-Lite crossbar, arranged
identically to the 4:10 crossbar on RP2040, but easier to show in the diagram.
Figure 5. A 2:3 AHB-
Lite crossbar. Each
upstream port
connects to a splitter,
which routes bus
requests toward one
of the 3 downstream
ports, and routes
responses back. Each
downstream port
connects to an arbiter,
which safely manages
concurrent access to
the port.
The crossbar is built from two components:
•
Splitters
◦
Perform coarse address decode
◦
Route requests (addresses, write data) to the downstream port indicated by the initial address decode
◦
Route responses (read data, bus errors) from the correct arbiter back to the upstream port
•
Arbiters
◦
Manage concurrent requests to a downstream port
◦
Route responses (read data, bus errors) to the correct splitter
◦
Implement bus priority rules
The main crossbar on RP2040 consists of 4 1:10 splitters and 10 4:1 arbiters, with a mesh of 40 AHB-Lite bus channels
between them. Note that, as AHB-Lite is a pipelined bus, the splitter may be routing back a response to an earlier
request from downstream port A, whilst a new request to downstream port B is already in progress. This does not incur
any cycle penalty.
2.1.1.1. Bus Priority
The arbiters in the main AHB-Lite crossbar implement a two-level bus priority scheme. Priority levels are configured per-
master, using the BUS_PRIORITY register in the BUSCTRL register block.
When there are multiple simultaneous accesses to same arbiter, any requests from high-priority masters (priority level
1) will be considered before any requests from low-priority masters (priority 0). If multiple masters of the same priority
level attempt to access the same slave simultaneously, a round-robin tie break is applied, i.e. the arbiter grants access
to each master in turn.
RP2040 Datasheet
2.1. Bus Fabric 16