Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 186. PICOBOOT
Exclusive access
command structure
Offset Name Value / Description
0x08 bCmdId 0x01 (EXCLUSIVE_ACCESS)
0x09 bCmdSize 0x01
0x0c dTransferLength 0x00000000
0x10 bExclusive NOT_EXCLUSIVE (0) No restriction on USB Mass Storage operation
EXCLUSIVE (1) Disable USB Mass Storage writes (the host should
see them as write protect failures, but in any case
any active UF2 download will be aborted)
EXCLUSIVE_AND_EJECT
(2)
Lock the USB Mass Storage Interface out by
marking the drive media as not present (ejecting
the drive)
2.8.4.4.2. REBOOT (0x02)
Reboots the RP2040 out of BOOTSEL mode. Note that BOOTSEL mode might be re-entered if rebooting to flash and no
valid second stage bootloader is found.
Table 187. PICOBOOT
Reboot access
command structure
Offset Name Value / Description
0x08 bCmdId 0x02 (REBOOT)
0x09 bCmdSize 0x0c
0x0c dTransferLength 0x00000000
0x10 dPC The address to start executing from. Valid values are:
0x00000000 Reboot via the standard
Flash boot mechanism
RAM address Reboot via watchdog and
start executing at the
specified address in RAM
0x14 dSP Initial stack pointer post reboot (only used if booting into
RAM)
0x18 dDelayMS Number of milliseconds to delay prior to reboot
2.8.4.4.3. FLASH_ERASE (0x03)
Erases a contiguous range of flash sectors.
Table 188. PICOBOOT
Flash erase command
structure
Offset Name Value / Description
0x08 bCmdId 0x03 (FLASH_ERASE)
0x09 bCmdSize 0x08
0x0c dTransferLength 0x00000000
0x10 dAddr The address in flash to erase, starting at this location. This must be sector
(4K) aligned
0x14 dSize The number of bytes to erase. This must an exact multiple number of sectors
(4K)
RP2040 Datasheet
2.8. Bootrom 174