Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
2.8.4.4.4. READ (0x84)
Read a contiguous memory (Flash or RAM or ROM) range from the RP2040
Table 189. PICOBOOT
Read memory
command (Flash,
RAM, ROM) structure
Offset Name Value / Description
0x08 bCmdId 0x84 (READ)
0x09 bCmdSize 0x08
0x0c dTransferLength Must be the same as dSize
0x10 dAddr The address to read from. May be in Flash or RAM or ROM
0x14 dSize The number of bytes to read
2.8.4.4.5. WRITE (0x05)
Writes a contiguous memory range of memory (Flash or RAM) on the RP2040.
Table 190. PICOBOOT
Write memory
command (Flash,
RAM) structure
Offset Name Value / Description
0x08 bCmdId 0x05 (WRITE)
0x09 bCmdSize 0x08
0x0c dTransferLength Must be the same as dSize
0x10 dAddr The address to write from. May be in Flash or RAM, however must be page
(256 byte) aligned if in Flash. Note the flash must be erased first or the results
are undefined.
0x14 dSize The number of bytes to write. If writing to flash and the size is not an exact
multiple of pages (256 bytes) then the last page is zero-filled to the end.
2.8.4.4.6. EXIT_XIP (0x06)
Exit Flash XIP mode. This first initialises the SSI for serial transfers, and then issues the XIP exit sequence given in
Section 2.8.1.2, to attempt to make the flash responsive to standard serial SPI commands. The SSI is configured with a
fixed clock divisor of /6, so the USB bootloader will drive SCLK at 8 MHz.
Table 191. PICOBOOT
Exit Execute in place
(XIP) command
structure
Offset Name Value / Description
0x08 bCmdId 0x06 (EXIT_XIP)
0x09 bCmdSize 0x00
0x0c dTransferLength 0x00000000
2.8.4.4.7. ENTER_XIP (0x07)
Enter Flash XIP mode. This configures the SSI to issue a standard 03h serial read command, with 24 address clocks and
32 data clocks, for every XIP access. This is a slow but very widely supported way to read flash. The intent of this
function is to make flash easily accessible (i.e. just access addresses in the 0x10…… segment) without having to know
the details of exactly what kind of flash is connected. This mode is suitable for executing code from flash, but is much
slower than e.g. QSPI XIP access.
Table 192. PICOBOOT
Enter Execute in place
(XIP) command
Offset Name Value / Description
0x08 bCmdId 0x07 (ENTER_XIP)
RP2040 Datasheet
2.8. Bootrom 175