Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Description
0x04 dStatusCode OK (0) The command completed successfully (or is in still in
progress)
UNKNOWN_CMD (1) The ID of the command was not recognized
INVALID_CMD_LENGTH (2) The length of the command request was incorrect
INVALID_TRANSFER_LENG
TH (3)
The data transfer length was incorrect given the
command
INVALID_ADDRESS (4) The address specified was invalid for the command type;
i.e. did not match the type Flash/RAM that the command
was expecting
BAD_ALIGNMENT (5) The address specified was not correctly aligned according
to the requirements of the command
INTERLEAVED_WRITE (6) A Mass Storage Interface UF2 write has interfered with the
current operation. The command was abandoned with
unknown status. Note this will not happen if you have
exclusive access.
REBOOTING (7) The device is in the process of rebooting, so the command
has been ignored.
UNKNOWN_ERROR (8) Some other error occurred.
0x08 bCmdId The ID of the command
0x09 bInProgress 1 if the command is still in
progress
0 otherwise
0x0a reserved (6 zero bytes)
2.9. Power Supplies
RP2040 requires five separate power supplies. However, in most applications, several of these can be combined and
connected to a single power source. In a typical application, only a single 3.3V supply will be required. See Section
2.9.7.1, “Single 3.3V Supply”.
The power supplies and a number of potential power supply schemes are described in the following sections. Detailed
power supply parameters are provided in Section 5.3, “Power Supplies”.
2.9.1. Digital IO Supply (IOVDD)
IOVDD supplies the chip’s digital IO, and should be powered at a nominal voltage between 1.8V and 3.3V. The supply
voltage sets the external signal level for the digital IO and should be chosen based on the signal level required. See
Section 5.2.3, “Pin Specifications” for details. All digital IOs share the same power supply and operate at the same
signal level.
IOVDD should be decoupled with a 100nF capacitor close to each of the chip’s IOVDD pins.
RP2040 Datasheet
2.9. Power Supplies 178