Datasheet


CAUTION
If the digital IO is powered at a nominal 1.8V, the IO input thresholds should be adjusted via the VOLTAGE_SELECT
register. By default, the IO input thresholds are valid when the digital IO is powered at a nominal voltage between
2.5V and 3.3V. See Section 2.19, “GPIO” for details. Powering the IO at 1.8V with input thresholds set for a 2.5V to
3.3V supply is a safe operating mode, but will result in input thresholds that do not meet specification. Powering the
IO at voltages greater than a nominal 1.8V with input thresholds set for a 1.8V supply may result in damage to the
chip.
2.9.2. Digital Core Supply (DVDD)
DVDD supplies the chip’s core digital logic, and should be powered at a nominal 1.1V. A dedicated on-chip voltage
regulator is provided to allow DVDD to be generated from the digital IO supply (IOVDD) or another nominally 1.8V to
3.3V supply. The connection between the output pin of the on-chip regulator (VREG_VOUT) and the DVDD supply pins is
made off-chip, allowing DVDD to be powered from an off-chip power source if required.
DVDD should be decoupled with a 100nF capacitor close to each of the chip’s DVDD pins.
2.9.3. On-Chip Voltage Regulator Input Supply (VREG_VIN)
VREG_VIN is the input supply for the on-chip voltage regulator. It should be powered at a nominal voltage between 1.8V
and 3.3V. To reduce the number of external power supplies, VREG_VIN can use the same power source as the digital IO
supply (IOVDD).
A 1μF capacitor should be connected between VREG_VIN and ground close to the chip’s VREG_VIN pin.

CAUTION
VREG_VIN also powers the chip’s power-on reset and brown-out detection blocks, so it must be powered even if the
on-chip voltage regulator is not used.
For more details on the on-chip voltage regulator see Section 2.10, “Core Supply Regulator”.
2.9.4. USB PHY Supply (USB_VDD)
USB_VDD supplies the chip’s USB PHY, and should be powered at a nominal 3.3V. To reduce the number of external
power supplies, USB_VDD can use the same power source as the digital IO supply (IOVDD), assuming IOVDD is also
powered at 3.3V. If IOVDD is not powered at 3.3V, a separate 3.3V supply will be required for the USB PHY, see Section
2.9.7.3, “1.8V Digital IO with Functional USB and ADC”. In applications where the USB PHY is never used, USB_VDD can
be tied to any supply with a nominal voltage between 1.8V and 3.3V. See Section 2.9.7.4, “Single 1.8V Supply” for an
example. USB_VDD should not be left unconnected.
USB_VDD should be decoupled with a 100nF capacitor close to the chip’s USB_VDD pin.
2.9.5. ADC Supply (ADC_AVDD)
ADC_AVDD supplies the chip’s Analogue to Digital Converter (ADC). It can be powered at a nominal voltage between
1.8V and 3.3V, but the performance of the ADC will be compromised at voltages below 2.97V. To reduce the number of
external power supplies, ADC_AVDD can use from the same power source as the digital IO supply (IOVDD).
RP2040 Datasheet
2.9. Power Supplies 179