Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
NOTE
It is safe to supply ADC_AVDD at a higher or lower voltage than IOVDD, e.g. to power the ADC at 3.3V, for optimum
performance, while supporting 1.8V signal levels on the digital IO. But the voltage on the ADC analogue inputs must
not exceed IOVDD, e.g. if IOVDD is powered at 1.8V, the voltage on the ADC inputs should be limited to 1.8V.
Voltages greater than IOVDD will result in leakage currents through the ESD protection diodes. See Section 5.2.3,
“Pin Specifications” for details.
ADC_AVDD should be decoupled with a 100nF capacitor close to the chip’s ADC_AVDD pin.
2.9.6. Power Supply Sequencing
RP2040’s power supplies may be powered up or down in any order. However, small transient currents may flow in the
ADC supply (ADC_AVDD) if it is powered up before, or powered down after, the digital core supply (DVDD). This will not
damage the chip, but can be avoided by powering up DVDD before or at the same time as ADC_AVDD, and powering
down DVDD after or at the same time as ADC_AVDD. In the most common power supply scheme, where the chip is
powered from a single 3.3V supply, DVDD will be powered up shortly after ADC_AVDD due to the startup time of the on-
chip voltage regulator. This is acceptable behaviour. See Section 2.9.7.1, “Single 3.3V Supply”.
2.9.7. Power Supply Schemes
2.9.7.1. Single 3.3V Supply
In most applications, RP2040 will be powered from a single 3.3V supply, as shown in Figure 16. The digital IO (IOVDD),
USB PHY (USB_VDD) and ADC (ADC_AVDD) will be powered directly from the 3.3V supply, and the 1.1V digital core
supply (DVDD) will be regulated from the 3.3V supply by the on-chip voltage regulator. Note that the regulator output pin
(VREG_VOUT) must be connected to the chip’s DVDD pins off-chip.
For more details on the on-chip voltage regulator see Section 2.10, “Core Supply Regulator”.
Figure 16. powering
the chip from a single
3.3V supply
(simplified diagram
omitting decoupling
components)
RP2040 Datasheet
2.9. Power Supplies 180