Datasheet

Figure 21. The chip-
level reset subsystem
2.12.2. Power-on Reset
The power-on reset block makes sure the chip starts up cleanly when power is first applied by holding it in reset until the
digital core supply (DVDD) can reliably power the chip’s core logic. The block holds its por_n output low until DVDD has
been above the power-on reset threshold (DVDD
TH.POR
) for a period greater than the power-on reset assertion delay
(t
POR.ASSERT
). Once high, por_n remains high even if DVDD subsequently falls below DVDD
TH.POR
, unless brown-out detection
is enabled. The behaviour of por_n when power is applied is shown in Figure 22.
DVDD
TH.POR
is fixed at a nominal 0.957V, which should result in a threshold between 0.924V and 0.99V. The threshold
assumes a nominal DVDD of 1.1V at initial power-on, and por_n may never go high if a lower voltage is used. Once the
chip is out of reset, DVDD can be reduced without por_n going low, as long as brown-out detection has been disabled or
a suitable threshold voltage has been set.
DVDD
por_n
DVDD
TH.POR
t
POR.ASSERT
Figure 22. A power-on
reset cycle
2.12.2.1. Detailed Specifications
RP2040 Datasheet
2.12. Chip-Level Reset 191