Datasheet

•
Crystal Oscillator reset is deasserted. The crystal oscillator is not started at this point, so rst_done is asserted
instantly.
•
clk_ref and clk_sys clock generators are taken out of reset. In the initial configuration clk_ref is running from the
ring oscillator with no divider. clk_sys is running from clk_ref. These clocks are needed for the rest of the sequence
to progress.
The rest of the sequence is fairly simple, with the following coming out of reset in order one by one:
•
Reset Controller - used to reset all non-boot peripherals
•
Chip-Level Reset and Voltage Regulator registers - used by the bootrom to check the boot state of the chip. In
particular, the PSM_RESTART_FLAG flag in the CHIP_RESET register can be set via SWD to indicate to the boot code that
there is bad code in flash and it should stop executing. The reset state of the CHIP_RESET register is determined
by the Chip-Level Reset subsystem and is not affected by reset coming from the power-on state machine
•
XIP (Execute-In-Place) - used by the bootrom to execute code from an external SPI flash
•
ROM and SRAM - Boot code is executed from the ROM. SRAM is used by processors and Bus Fabric.
•
Bus Fabric - Allows the processors to communicate with peripherals
•
Processor complex - Finally the processors can start running
The final thing to come out of reset is the processor complex. This includes both core0 and core1. Both cores will start
executing the bootcode from ROM. One of the first things the bootrom does is read the core id. At this point, core1 will
go to sleep leaving core0 to continue with the bootrom execution. The processor complex has its own reset control and
various low-power modes which is why both the core0 and core1 resets are deasserted, despite only core0 being needed
for the bootrom.
2.13.3. Register Control
The power-on state machine is a fully automated piece of hardware. It requires no input from the user to work. There
are register controls that can be used to override and see the status of the power-on state machine. This allows
hardware blocks in the power-on state machine to be reset by software if necessary. There is also a WDSEL register which
is used to control what is reset by a Watchdog reset.
2.13.4. Interaction with Watchdog
The power-on state machine can be restarted from a software-programmable position if the Watchdog fires. For
example, in the case the processor is stuck in an infinite loop, or the programmer has somehow misconfigured the chip.
It is important to note that if a peripheral in the power-on state machine has the WDSEL bit set, every peripheral after it in
the power-on sequence will also be reset because the rst_done of the selected peripheral will be deasserted, asserting
rst_n for the remaining peripherals.
2.13.5. List of Registers
The PSM registers start at a base address of 0x40010000 (defined as PSM_BASE in SDK).
Table 207. List of PSM
registers
Offset Name Info
0x0 FRCE_ON Force block out of reset (i.e. power it on)
0x4 FRCE_OFF Force into reset (i.e. power it off)
0x8 WDSEL Set to 1 if this peripheral should be reset when the watchdog
fires.
0xc DONE Indicates the peripheral’s registers are ready to access.
RP2040 Datasheet
2.13. Power-On State Machine 196