Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
1 BUSCTRL RW 0x0
0 ADC RW 0x0
RESETS: RESET_DONE Register
Offset: 0x8
Description
Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the
peripheral’s registers are ready to be accessed.
Table 215.
RESET_DONE Register
Bits Name Description Type Reset
31:25 Reserved. - - -
24 USBCTRL RO 0x0
23 UART1 RO 0x0
22 UART0 RO 0x0
21 TIMER RO 0x0
20 TBMAN RO 0x0
19 SYSINFO RO 0x0
18 SYSCFG RO 0x0
17 SPI1 RO 0x0
16 SPI0 RO 0x0
15 RTC RO 0x0
14 PWM RO 0x0
13 PLL_USB RO 0x0
12 PLL_SYS RO 0x0
11 PIO1 RO 0x0
10 PIO0 RO 0x0
9 PADS_QSPI RO 0x0
8 PADS_BANK0 RO 0x0
7 JTAG RO 0x0
6 IO_QSPI RO 0x0
5 IO_BANK0 RO 0x0
4 I2C1 RO 0x0
3 I2C0 RO 0x0
2 DMA RO 0x0
1 BUSCTRL RO 0x0
0 ADC RO 0x0
RP2040 Datasheet
2.14. Subsystem Resets 203