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The PLLs are not affected by SLEEP mode. If the user wants to save power in SLEEP mode then all clock generators
must be switched away from the PLLs and they must be stopped in software before entering SLEEP mode. The PLLs
are not stopped and restarted automatically when entering and exiting DORMANT mode. If they are left running on entry
to DORMANT mode they will be corrupted and will generate out of control clocks that will consume power
unnecessarily. This happens because their reference clock from XOSC will be stopped. It is therefore essential to switch
all clock generators away from the PLLs and stop the PLLs in software before entering DORMANT mode.
2.15.3. Clock Generators
The clock generators are built on a standard design which incorporates clock source multiplexing, division, duty cycle
correction and SLEEP mode enabling. To save chip area and power, the individual clock generators do not support all
features.
Figure 30. A generic
clock generator
2.15.3.1. Instances
RP2040 has several clock generators which are listed below.
Table 216. RP2040
clock generators
Clock Description Nominal Frequency
clk_gpout0
Clock output to GPIO. Can be used to
clock external devices or debug on
chip clocks with a logic analyser or
oscilloscope.
N/A
clk_gpout1
clk_gpout2
clk_gpout3
clk_ref
Reference clock that is always running
unless in DORMANT mode. Runs from
Ring Oscillator (ROSC) at power-up
but can be switched to Crystal
Oscillator (XOSC) for more accuracy.
6 - 12MHz
clk_sys
System clock that is always running
unless in DORMANT mode. Runs from
clk_ref at power-up but is typically
switched to a PLL.
125MHz
clk_peri
Peripheral clock. Typically runs from
clk_sys but allows peripherals to run at
a consistent speed if clk_sys is
changed by software.
12 - 125MHz
clk_usb
USB reference clock. Must be 48MHz. 48MHz
clk_adc
ADC reference clock. Must be 48MHz. 48MHz
clk_rtc
RTC reference clock. The RTC divides
this clock to generate a 1 second
reference.
46875Hz
For a full list of clock sources for each clock generator see the appropriate CTRL register. For example, CLK_SYS_CTRL.
RP2040 Datasheet
2.15. Clocks 208