Datasheet

2.15.3.2. Multiplexers
All clock generators have a multiplexer referred to as the auxiliary (aux) mux. This mux has a conventional design
whose output will glitch when changing the select control. Two clock generators (clk_sys and clk_ref) have an additional
multiplexer, referred to as the glitchless mux. The glitchless mux can switch between clock sources without generating
a glitch on the output.
Clock glitches should be avoided at all costs because they may corrupt the logic running on that clock. This means that
any clock generator with only an aux mux must be disabled while switching the clock source. If the clock generator has
a glitchless mux (clk_sys and clk_ref), then the glitchless mux should switch away from the aux mux while changing the
aux mux source. The clock generators require 2 cycles of the source clock to stop the output and 2 cycles of the new
source to restart the output. The user must wait for the generator to stop before changing the auxiliary mux, and
therefore must be aware of the source clock frequency.
The glitchless mux is only implemented for always-on clocks. On RP2040 the always-on clocks are the reference clock
(clk_ref) and the system clock (clk_sys). Such clocks must run continuously unless the chip is in DORMANT mode. The
glitchless mux has a status output (SELECTED) which indicates which source is selected and can be read from
software to confirm that a change of clock source has been completed.
The recommended control sequences are as follows.
To switch the glitchless mux:
•
switch the glitchless mux to an alternate source
•
poll the SELECTED register until the switch is completed
To switch the auxiliary mux when the generator has a glitchless mux:
•
switch the glitchless mux to a source that isn’t the aux mux
•
poll the SELECTED register until the switch is completed
•
change the auxiliary mux select control
•
switch the glitchless mux back to the aux mux
•
if required, poll the SELECTED register until the switch is completed
To switch the auxiliary mux when the generator does not have a glitchless mux:
•
disable the clock divider
•
wait for the generated clock to stop (2 cycles of the clock source)
•
change the auxiliary mux select control
•
enable the clock divider
•
if required, wait for the clock generator to restart (2 cycles of the clock source)
See Section 2.15.6.1 for a code example of this.
2.15.3.3. Divider
A fully featured divider divides by 1 or a fractional number in the range 2.0 to 2^24-0.01. Fractional division is achieved
by toggling between 2 integer divisors therefore it yields a jittery clock which may not be suitable for some applications.
For example, when dividing by 2.4 the divider will divide by 2 for 3 cycles and by 3 for 2 cycles. For divisors with large
integer components the jitter will be much smaller and less critical.
RP2040 Datasheet
2.15. Clocks 209