Datasheet

registers, including those that control the clock enables.
clk_sys_clocks does not have a wake mode enable because disabling it would prevent the cores from accessing the
clocks control registers.
The gpclks do not have clock enables.
2.15.3.5.2. System Sleep Mode
System sleep mode is entered automatically when both cores are in sleep and the DMA has no outstanding
transactions. In system sleep mode, the clock enables described in the previous paragraphs are switched from the
WAKE_EN registers to the SLEEP_EN registers. The intention is to reduce power consumed in the clock distribution networks
when the chip is inactive. If the user has not configured the WAKE_EN and SLEEP_EN registers then system sleep will do
nothing.
There is little value in using system sleep without taking other measures to reduce power before the cores are put to
sleep. Things to consider include:
•
stop unused clock sources such as the PLLs and Crystal Oscillator
•
reduce the frequencies of generated clocks by increasing the clock divisors
•
stop external clocks
For maximum power saving when the chip is inactive, the user should consider DORMANT (see Section 2.11.3) mode in
which clocks are sourced from the Crystal Oscillator and/or the Ring Oscillator and those clock sources are stopped.
2.15.4. Frequency Counter
The frequency counter measures the frequency of internal and external clocks by counting the clock edges seen over a
test interval. The interval is defined by counting cycles of clk_ref which must be driven either from XOSC or from a
stable external source of known frequency.
The user can pick between accuracy and test time using the FC0_INTERVAL register. Table 217 shows the trade off.
Table 217. Frequency
Counter Test Interval
vs Accuracy
Interval Register Test Interval Accuracy
0 1 μs 2048 kHz
1 2 μs 1024 kHz
2 4 μs 512 kHz
3 8 μs 256 kHz
4 16 μs 128 kHz
5 32 μs 64 kHz
6 64 μs 32 kHz
7 125 μs 16 kHz
8 250 μs 8 kHz
9 500 μs 4 kHz
10 1 ms 2 kHz
11 2 ms 1 kHz
12 4 ms 500 Hz
13 8 ms 250 Hz
14 16 ms 125 Hz
RP2040 Datasheet
2.15. Clocks 211