Datasheet

And also a struct to describe the registers of a clock generator:
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2040/hardware_structs/include/hardware/structs/clocks.h Lines 34 - 38
34 typedef struct {
35 io_rw_32 ctrl;
36 io_rw_32 div;
37 io_rw_32 selected;
38 } clock_hw_t;
To configure a clock, we need to know the following pieces of information:
•
The frequency of the clock source
•
The mux / aux mux position of the clock source
•
The desired output frequency
The SDK provides clock_configure to configure a clock:
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 42 - 118
Ê42 bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t
Ê src_freq, uint32_t freq) {
Ê43 uint32_t div;
Ê44
Ê45 assert(src_freq >= freq);
Ê46
Ê47 if (freq > src_freq)
Ê48 return false;
Ê49
Ê50 // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
Ê51 div = (uint32_t) (((uint64_t) src_freq << 8) / freq);
Ê52
Ê53 clock_hw_t *clock = &clocks_hw->clk[clk_index];
Ê54
Ê55 // If increasing divisor, set divisor before source. Otherwise set source
Ê56 // before divisor. This avoids a momentary overspeed when e.g. switching
Ê57 // to a faster source and increasing divisor to compensate.
Ê58 if (div > clock->div)
Ê59 clock->div = div;
Ê60
Ê61 // If switching a glitchless slice (ref or sys) to an aux source, switch
Ê62 // away from aux *first* to avoid passing glitches when changing aux mux.
Ê63 // Assume (!!!) glitchless source 0 is no faster than the aux source.
Ê64 if (has_glitchless_mux(clk_index) && src ==
Ê CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) {
Ê65 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
Ê66 while (!(clock->selected & 1u))
Ê67 tight_loop_contents();
Ê68 }
Ê69 // If no glitchless mux, cleanly stop the clock to avoid glitches
Ê70 // propagating when changing aux mux. Note it would be a really bad idea
Ê71 // to do this on one of the glitchless clocks (clk_sys, clk_ref).
Ê72 else {
Ê73 // Disable clock. On clk_ref and clk_sys this does nothing,
Ê74 // all other clocks have the ENABLE bit in the same position.
Ê75 hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
Ê76 if (configured_freq[clk_index] > 0) {
Ê77 // Delay for 3 cycles of the target clock, for ENABLE propagation.
Ê78 // Note XOSC_COUNT is not helpful here because XOSC is not
Ê79 // necessarily running, nor is timer... so, 3 cycles per loop:
Ê80 uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1;
RP2040 Datasheet
2.15. Clocks 213