Datasheet

Ê81 asm volatile (
Ê82 ".syntax unified \n\t"
Ê83 "1: \n\t"
Ê84 "subs %0, #1 \n\t"
Ê85 "bne 1b"
Ê86 : "+r" (delay_cyc)
Ê87 );
Ê88 }
Ê89 }
Ê90
Ê91 // Set aux mux first, and then glitchless mux if this clock has one
Ê92 hw_write_masked(&clock->ctrl,
Ê93 (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
Ê94 CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS
Ê95 );
Ê96
Ê97 if (has_glitchless_mux(clk_index)) {
Ê98 hw_write_masked(&clock->ctrl,
Ê99 src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
100 CLOCKS_CLK_REF_CTRL_SRC_BITS
101 );
102 while (!(clock->selected & (1u << src)))
103 tight_loop_contents();
104 }
105
106 // Enable clock. On clk_ref and clk_sys this does nothing,
107 // all other clocks have the ENABLE bit in the same position.
108 hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
109
110 // Now that the source is configured, we can trust that the user-supplied
111 // divisor is a safe value.
112 clock->div = div;
113
114 // Store the configured frequency
115 configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
116
117 return true;
118 }
It is called in clocks_init for each clock. The following example shows the clk_sys configuration:
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 169 - 174
169 // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
170 clock_configure(clk_sys,
171 CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
172 CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
173 125 * MHZ,
174 125 * MHZ);
Once a clock is configured, clock_get_hz can be called to get the output frequency in Hz.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 208 - 210
208 uint32_t clock_get_hz(enum clock_index clk_index) {
209 return configured_freq[clk_index];
210 }
RP2040 Datasheet
2.15. Clocks 214