Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
NOTE
The frequency counter can also be used in a test mode. This allows the hardware to check if the frequency is within
a minimum frequency and a maximum frequency, set in FC0_MIN_KHZ and FC0_MAX_KHZ. In this mode, the PASS bit
in FC0_STATUS will be set when DONE is set if the frequency is within the specified range. Otherwise, either the FAST or
SLOW bit will be set.
If the programmer attempts to count a stopped clock, or the clock stops running then the DIED bit will be set. If any of
DIED, FAST, or SLOW are set then FAIL will be set.
2.15.6.3. Configuring a GPIO output clock
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 317 - 337
317 void clock_gpio_init(uint gpio, uint src, uint div) {
318 // Bit messy but it's as much code to loop through a lookup
319 // table. The sources for each gpout generators are the same
320 // so just call with the sources from GP0
321 uint gpclk = 0;
322 if (gpio == 21) gpclk = clk_gpout0;
323 else if (gpio == 23) gpclk = clk_gpout1;
324 else if (gpio == 24) gpclk = clk_gpout2;
325 else if (gpio == 25) gpclk = clk_gpout3;
326 else {
327 invalid_params_if(CLOCKS, true);
328 }
329
330 // Set up the gpclk generator
331 clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
332 CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
333 clocks_hw->clk[gpclk].div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB;
334
335 // Set gpio pin to gpclock function
336 gpio_set_function(gpio, GPIO_FUNC_GPCK);
337 }
2.15.6.4. Configuring a GPIO input clock
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 364 - 390
364 bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq,
Ê uint32_t freq) {
365 // Configure a clock to run from a GPIO input
366 uint gpin = 0;
367 if (gpio == 20) gpin = 0;
368 else if (gpio == 22) gpin = 1;
369 else {
370 invalid_params_if(CLOCKS, true);
371 }
372
373 // Work out sources. GPIN is always an auxsrc
374 uint src = 0;
375
376 // GPIN1 == GPIN0 + 1
377 uint auxsrc = gpin0_src[clk_index] + gpin;
378
RP2040 Datasheet
2.15. Clocks 216