Datasheet


NOTE
clk_sys is always sent to proc0 and proc1 during sleep mode as some logic needs to be clocked for the processor to
wake up again.
Pico Extras: https://github.com/raspberrypi/pico-extras/tree/master/src/rp2_common/pico_sleep/sleep.c Lines 106 - 122
106 void sleep_goto_sleep_until(datetime_t *t, rtc_callback_t callback) {
107 // We should have already called the sleep_run_from_dormant_source function
108 assert(dormant_source_valid(_dormant_source));
109
110 // Turn off all clocks when in sleep mode except for RTC
111 clocks_hw->sleep_en0 = CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS;
112 clocks_hw->sleep_en1 = 0x0;
113
114 rtc_set_alarm(t, callback);
115
116 uint save = scb_hw->scr;
117 // Enable deep sleep at the proc
118 scb_hw->scr = save | M0PLUS_SCR_SLEEPDEEP_BITS;
119
120 // Go to sleep
121 __wfi();
122 }
2.15.7. List of Registers
The Clocks registers start at a base address of 0x40008000 (defined as CLOCKS_BASE in SDK).
Table 218. List of
CLOCKS registers
Offset Name Info
0x00 CLK_GPOUT0_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x04 CLK_GPOUT0_DIV Clock divisor, can be changed on-the-fly
0x08 CLK_GPOUT0_SELECTED Indicates which SRC is currently selected by the glitchless mux
(one-hot).
0x0c CLK_GPOUT1_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x10 CLK_GPOUT1_DIV Clock divisor, can be changed on-the-fly
0x14 CLK_GPOUT1_SELECTED Indicates which SRC is currently selected by the glitchless mux
(one-hot).
0x18 CLK_GPOUT2_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x1c CLK_GPOUT2_DIV Clock divisor, can be changed on-the-fly
0x20 CLK_GPOUT2_SELECTED Indicates which SRC is currently selected by the glitchless mux
(one-hot).
0x24 CLK_GPOUT3_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x28 CLK_GPOUT3_DIV Clock divisor, can be changed on-the-fly
0x2c CLK_GPOUT3_SELECTED Indicates which SRC is currently selected by the glitchless mux
(one-hot).
0x30 CLK_REF_CTRL Clock control, can be changed on-the-fly (except for auxsrc)
0x34 CLK_REF_DIV Clock divisor, can be changed on-the-fly
RP2040 Datasheet
2.15. Clocks 218