Datasheet

Offset Name Info
0xa8 SLEEP_EN0 enable clock in sleep mode
0xac SLEEP_EN1 enable clock in sleep mode
0xb0 ENABLED0 indicates the state of the clock enable
0xb4 ENABLED1 indicates the state of the clock enable
0xb8 INTR Raw Interrupts
0xbc INTE Interrupt Enable
0xc0 INTF Interrupt Force
0xc4 INTS Interrupt status after masking & forcing
CLOCKS: CLK_GPOUT0_CTRL Register
Offset: 0x00
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 219.
CLK_GPOUT0_CTRL
Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20 NUDGE An edge on this signal shifts the phase of the output by 1
cycle of the input clock
This can be done at any time
RW 0x0
19:18 Reserved. - - -
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:13 Reserved. - - -
12 DC50 Enables duty cycle correction for odd divisors RW 0x0
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
9 Reserved. - - -
8:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 → clksrc_pll_sys
0x1 → clksrc_gpin0
0x2 → clksrc_gpin1
0x3 → clksrc_pll_usb
0x4 → rosc_clksrc
0x5 → xosc_clksrc
0x6 → clk_sys
0x7 → clk_usb
0x8 → clk_adc
0x9 → clk_rtc
0xa → clk_ref
RW 0x0
4:0 Reserved. - - -
RP2040 Datasheet
2.15. Clocks 220