Datasheet

CLOCKS: CLK_GPOUT0_DIV Register
Offset: 0x04
Description
Clock divisor, can be changed on-the-fly
Table 220.
CLK_GPOUT0_DIV
Register
Bits Name Description Type Reset
31:8 INT
Integer component of the divisor, 0 → divide by 2^16
RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLOCKS: CLK_GPOUT0_SELECTED Register
Offset: 0x08
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
Table 221.
CLK_GPOUT0_SELECT
ED Register
Bits Description Type Reset
31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present,
not SRC) so this register is hardwired to 0x1.
RO 0x00000001
CLOCKS: CLK_GPOUT1_CTRL Register
Offset: 0x0c
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 222.
CLK_GPOUT1_CTRL
Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20 NUDGE An edge on this signal shifts the phase of the output by 1
cycle of the input clock
This can be done at any time
RW 0x0
19:18 Reserved. - - -
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:13 Reserved. - - -
12 DC50 Enables duty cycle correction for odd divisors RW 0x0
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
9 Reserved. - - -
RP2040 Datasheet
2.15. Clocks 221