Datasheet

Bits Name Description Type Reset
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:13 Reserved. - - -
12 DC50 Enables duty cycle correction for odd divisors RW 0x0
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
9 Reserved. - - -
8:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 → clksrc_pll_sys
0x1 → clksrc_gpin0
0x2 → clksrc_gpin1
0x3 → clksrc_pll_usb
0x4 → rosc_clksrc_ph
0x5 → xosc_clksrc
0x6 → clk_sys
0x7 → clk_usb
0x8 → clk_adc
0x9 → clk_rtc
0xa → clk_ref
RW 0x0
4:0 Reserved. - - -
CLOCKS: CLK_GPOUT2_DIV Register
Offset: 0x1c
Description
Clock divisor, can be changed on-the-fly
Table 226.
CLK_GPOUT2_DIV
Register
Bits Name Description Type Reset
31:8 INT
Integer component of the divisor, 0 → divide by 2^16
RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLOCKS: CLK_GPOUT2_SELECTED Register
Offset: 0x20
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
Table 227.
CLK_GPOUT2_SELECT
ED Register
Bits Description Type Reset
31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present,
not SRC) so this register is hardwired to 0x1.
RO 0x00000001
CLOCKS: CLK_GPOUT3_CTRL Register
Offset: 0x24
RP2040 Datasheet
2.15. Clocks 223