Datasheet

Table 233.
CLK_REF_SELECTED
Register
Bits Description Type Reset
31:0 The glitchless multiplexer does not switch instantaneously (to avoid glitches),
so software should poll this register to wait for the switch to complete. This
register contains one decoded bit for each of the clock sources enumerated in
the CTRL SRC field. At most one of these bits will be set at any time, indicating
that clock is currently present at the output of the glitchless mux. Whilst
switching is in progress, this register may briefly show all-0s.
RO 0x00000001
CLOCKS: CLK_SYS_CTRL Register
Offset: 0x3c
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 234.
CLK_SYS_CTRL
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 → clksrc_pll_sys
0x1 → clksrc_pll_usb
0x2 → rosc_clksrc
0x3 → xosc_clksrc
0x4 → clksrc_gpin0
0x5 → clksrc_gpin1
RW 0x0
4:1 Reserved. - - -
0 SRC Selects the clock source glitchlessly, can be changed on-
the-fly
0x0 → clk_ref
0x1 → clksrc_clk_sys_aux
RW 0x0
CLOCKS: CLK_SYS_DIV Register
Offset: 0x40
Description
Clock divisor, can be changed on-the-fly
Table 235.
CLK_SYS_DIV Register
Bits Name Description Type Reset
31:8 INT
Integer component of the divisor, 0 → divide by 2^16
RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLOCKS: CLK_SYS_SELECTED Register
Offset: 0x44
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
RP2040 Datasheet
2.15. Clocks 226