Datasheet

Bits Name Description Type Reset
20 NUDGE An edge on this signal shifts the phase of the output by 1
cycle of the input clock
This can be done at any time
RW 0x0
19:18 Reserved. - - -
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:12 Reserved. - - -
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
9:8 Reserved. - - -
7:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 → clksrc_pll_usb
0x1 → clksrc_pll_sys
0x2 → rosc_clksrc_ph
0x3 → xosc_clksrc
0x4 → clksrc_gpin0
0x5 → clksrc_gpin1
RW 0x0
4:0 Reserved. - - -
CLOCKS: CLK_USB_DIV Register
Offset: 0x58
Description
Clock divisor, can be changed on-the-fly
Table 240.
CLK_USB_DIV Register
Bits Name Description Type Reset
31:10 Reserved. - - -
9:8 INT
Integer component of the divisor, 0 → divide by 2^16
RW 0x1
7:0 Reserved. - - -
CLOCKS: CLK_USB_SELECTED Register
Offset: 0x5c
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
RP2040 Datasheet
2.15. Clocks 228