Datasheet

Table Of Contents
Offset: 0x68
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
Table 244.
CLK_ADC_SELECTED
Register
Bits Description Type Reset
31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present,
not SRC) so this register is hardwired to 0x1.
RO 0x00000001
CLOCKS: CLK_RTC_CTRL Register
Offset: 0x6c
Description
Clock control, can be changed on-the-fly (except for auxsrc)
Table 245.
CLK_RTC_CTRL
Register
Bits Name Description Type Reset
31:21 Reserved. - - -
20 NUDGE An edge on this signal shifts the phase of the output by 1
cycle of the input clock
This can be done at any time
RW 0x0
19:18 Reserved. - - -
17:16 PHASE This delays the enable signal by up to 3 cycles of the input
clock
This must be set before the clock is enabled to have any
effect
RW 0x0
15:12 Reserved. - - -
11 ENABLE Starts and stops the clock generator cleanly RW 0x0
10 KILL Asynchronously kills the clock generator RW 0x0
9:8 Reserved. - - -
7:5 AUXSRC Selects the auxiliary clock source, will glitch when
switching
0x0 clksrc_pll_usb
0x1 clksrc_pll_sys
0x2 rosc_clksrc_ph
0x3 xosc_clksrc
0x4 clksrc_gpin0
0x5 clksrc_gpin1
RW 0x0
4:0 Reserved. - - -
CLOCKS: CLK_RTC_DIV Register
Offset: 0x70
Description
Clock divisor, can be changed on-the-fly
RP2040 Datasheet
2.15. Clocks 230