Datasheet

Table 246.
CLK_RTC_DIV Register
Bits Name Description Type Reset
31:8 INT
Integer component of the divisor, 0 → divide by 2^16
RW 0x000001
7:0 FRAC Fractional component of the divisor RW 0x00
CLOCKS: CLK_RTC_SELECTED Register
Offset: 0x74
Description
Indicates which SRC is currently selected by the glitchless mux (one-hot).
Table 247.
CLK_RTC_SELECTED
Register
Bits Description Type Reset
31:0 This slice does not have a glitchless mux (only the AUX_SRC field is present,
not SRC) so this register is hardwired to 0x1.
RO 0x00000001
CLOCKS: CLK_SYS_RESUS_CTRL Register
Offset: 0x78
Table 248.
CLK_SYS_RESUS_CTR
L Register
Bits Name Description Type Reset
31:17 Reserved. - - -
16 CLEAR For clearing the resus after the fault that triggered it has
been corrected
RW 0x0
15:13 Reserved. - - -
12 FRCE Force a resus, for test purposes only RW 0x0
11:9 Reserved. - - -
8 ENABLE Enable resus RW 0x0
7:0 TIMEOUT This is expressed as a number of clk_ref cycles
and must be >= 2x clk_ref_freq/min_clk_tst_freq
RW 0xff
CLOCKS: CLK_SYS_RESUS_STATUS Register
Offset: 0x7c
Table 249.
CLK_SYS_RESUS_STA
TUS Register
Bits Name Description Type Reset
31:1 Reserved. - - -
0 RESUSSED Clock has been resuscitated, correct the error then send
ctrl_clear=1
RO 0x0
CLOCKS: FC0_REF_KHZ Register
Offset: 0x80
RP2040 Datasheet
2.15. Clocks 231