Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 255. FC0_SRC
Register
Bits Description Type Reset
31:8 Reserved. - -
7:0 Clock sent to frequency counter, set to 0 when not required
Writing to this register initiates the frequency count
0x00 → NULL
0x01 → pll_sys_clksrc_primary
0x02 → pll_usb_clksrc_primary
0x03 → rosc_clksrc
0x04 → rosc_clksrc_ph
0x05 → xosc_clksrc
0x06 → clksrc_gpin0
0x07 → clksrc_gpin1
0x08 → clk_ref
0x09 → clk_sys
0x0a → clk_peri
0x0b → clk_usb
0x0c → clk_adc
0x0d → clk_rtc
RW 0x00
CLOCKS: FC0_STATUS Register
Offset: 0x98
Description
Frequency counter status
Table 256.
FC0_STATUS Register
Bits Name Description Type Reset
31:29 Reserved. - - -
28 DIED Test clock stopped during test RO 0x0
27:25 Reserved. - - -
24 FAST Test clock faster than expected, only valid when
status_done=1
RO 0x0
23:21 Reserved. - - -
20 SLOW Test clock slower than expected, only valid when
status_done=1
RO 0x0
19:17 Reserved. - - -
16 FAIL Test failed RO 0x0
15:13 Reserved. - - -
12 WAITING Waiting for test clock to start RO 0x0
11:9 Reserved. - - -
8 RUNNING Test running RO 0x0
7:5 Reserved. - - -
4 DONE Test complete RO 0x0
3:1 Reserved. - - -
0 PASS Test passed RO 0x0
CLOCKS: FC0_RESULT Register
RP2040 Datasheet
2.15. Clocks 233