Datasheet

Table Of Contents
Offset: 0x9c
Description
Result of frequency measurement, only valid when status_done=1
Table 257.
FC0_RESULT Register
Bits Name Description Type Reset
31:30 Reserved. - - -
29:5 KHZ RO 0x0000000
4:0 FRAC RO 0x00
CLOCKS: WAKE_EN0 Register
Offset: 0xa0
Description
enable clock in wake mode
Table 258. WAKE_EN0
Register
Bits Name Description Type Reset
31 CLK_SYS_SRAM3 RW 0x1
30 CLK_SYS_SRAM2 RW 0x1
29 CLK_SYS_SRAM1 RW 0x1
28 CLK_SYS_SRAM0 RW 0x1
27 CLK_SYS_SPI1 RW 0x1
26 CLK_PERI_SPI1 RW 0x1
25 CLK_SYS_SPI0 RW 0x1
24 CLK_PERI_SPI0 RW 0x1
23 CLK_SYS_SIO RW 0x1
22 CLK_SYS_RTC RW 0x1
21 CLK_RTC_RTC RW 0x1
20 CLK_SYS_ROSC RW 0x1
19 CLK_SYS_ROM RW 0x1
18 CLK_SYS_RESETS RW 0x1
17 CLK_SYS_PWM RW 0x1
16 CLK_SYS_PSM RW 0x1
15 CLK_SYS_PLL_USB RW 0x1
14 CLK_SYS_PLL_SYS RW 0x1
13 CLK_SYS_PIO1 RW 0x1
12 CLK_SYS_PIO0 RW 0x1
11 CLK_SYS_PADS RW 0x1
10 CLK_SYS_VREG_AND_CHIP_RESET RW 0x1
9 CLK_SYS_JTAG RW 0x1
8 CLK_SYS_IO RW 0x1
RP2040 Datasheet
2.15. Clocks 234