Datasheet

Bits Name Description Type Reset
7 CLK_SYS_I2C1 RW 0x1
6 CLK_SYS_I2C0 RW 0x1
5 CLK_SYS_DMA RW 0x1
4 CLK_SYS_BUSFABRIC RW 0x1
3 CLK_SYS_BUSCTRL RW 0x1
2 CLK_SYS_ADC RW 0x1
1 CLK_ADC_ADC RW 0x1
0 CLK_SYS_CLOCKS RW 0x1
CLOCKS: WAKE_EN1 Register
Offset: 0xa4
Description
enable clock in wake mode
Table 259. WAKE_EN1
Register
Bits Name Description Type Reset
31:15 Reserved. - - -
14 CLK_SYS_XOSC RW 0x1
13 CLK_SYS_XIP RW 0x1
12 CLK_SYS_WATCHDOG RW 0x1
11 CLK_USB_USBCTRL RW 0x1
10 CLK_SYS_USBCTRL RW 0x1
9 CLK_SYS_UART1 RW 0x1
8 CLK_PERI_UART1 RW 0x1
7 CLK_SYS_UART0 RW 0x1
6 CLK_PERI_UART0 RW 0x1
5 CLK_SYS_TIMER RW 0x1
4 CLK_SYS_TBMAN RW 0x1
3 CLK_SYS_SYSINFO RW 0x1
2 CLK_SYS_SYSCFG RW 0x1
1 CLK_SYS_SRAM5 RW 0x1
0 CLK_SYS_SRAM4 RW 0x1
CLOCKS: SLEEP_EN0 Register
Offset: 0xa8
Description
enable clock in sleep mode
Table 260. SLEEP_EN0
Register
Bits Name Description Type Reset
31 CLK_SYS_SRAM3 RW 0x1
RP2040 Datasheet
2.15. Clocks 235