Datasheet

Table 261. SLEEP_EN1
Register
Bits Name Description Type Reset
31:15 Reserved. - - -
14 CLK_SYS_XOSC RW 0x1
13 CLK_SYS_XIP RW 0x1
12 CLK_SYS_WATCHDOG RW 0x1
11 CLK_USB_USBCTRL RW 0x1
10 CLK_SYS_USBCTRL RW 0x1
9 CLK_SYS_UART1 RW 0x1
8 CLK_PERI_UART1 RW 0x1
7 CLK_SYS_UART0 RW 0x1
6 CLK_PERI_UART0 RW 0x1
5 CLK_SYS_TIMER RW 0x1
4 CLK_SYS_TBMAN RW 0x1
3 CLK_SYS_SYSINFO RW 0x1
2 CLK_SYS_SYSCFG RW 0x1
1 CLK_SYS_SRAM5 RW 0x1
0 CLK_SYS_SRAM4 RW 0x1
CLOCKS: ENABLED0 Register
Offset: 0xb0
Description
indicates the state of the clock enable
Table 262. ENABLED0
Register
Bits Name Description Type Reset
31 CLK_SYS_SRAM3 RO 0x0
30 CLK_SYS_SRAM2 RO 0x0
29 CLK_SYS_SRAM1 RO 0x0
28 CLK_SYS_SRAM0 RO 0x0
27 CLK_SYS_SPI1 RO 0x0
26 CLK_PERI_SPI1 RO 0x0
25 CLK_SYS_SPI0 RO 0x0
24 CLK_PERI_SPI0 RO 0x0
23 CLK_SYS_SIO RO 0x0
22 CLK_SYS_RTC RO 0x0
21 CLK_RTC_RTC RO 0x0
20 CLK_SYS_ROSC RO 0x0
19 CLK_SYS_ROM RO 0x0
18 CLK_SYS_RESETS RO 0x0
RP2040 Datasheet
2.15. Clocks 237