Datasheet

Bits Name Description Type Reset
17 CLK_SYS_PWM RO 0x0
16 CLK_SYS_PSM RO 0x0
15 CLK_SYS_PLL_USB RO 0x0
14 CLK_SYS_PLL_SYS RO 0x0
13 CLK_SYS_PIO1 RO 0x0
12 CLK_SYS_PIO0 RO 0x0
11 CLK_SYS_PADS RO 0x0
10 CLK_SYS_VREG_AND_CHIP_RESET RO 0x0
9 CLK_SYS_JTAG RO 0x0
8 CLK_SYS_IO RO 0x0
7 CLK_SYS_I2C1 RO 0x0
6 CLK_SYS_I2C0 RO 0x0
5 CLK_SYS_DMA RO 0x0
4 CLK_SYS_BUSFABRIC RO 0x0
3 CLK_SYS_BUSCTRL RO 0x0
2 CLK_SYS_ADC RO 0x0
1 CLK_ADC_ADC RO 0x0
0 CLK_SYS_CLOCKS RO 0x0
CLOCKS: ENABLED1 Register
Offset: 0xb4
Description
indicates the state of the clock enable
Table 263. ENABLED1
Register
Bits Name Description Type Reset
31:15 Reserved. - - -
14 CLK_SYS_XOSC RO 0x0
13 CLK_SYS_XIP RO 0x0
12 CLK_SYS_WATCHDOG RO 0x0
11 CLK_USB_USBCTRL RO 0x0
10 CLK_SYS_USBCTRL RO 0x0
9 CLK_SYS_UART1 RO 0x0
8 CLK_PERI_UART1 RO 0x0
7 CLK_SYS_UART0 RO 0x0
6 CLK_PERI_UART0 RO 0x0
5 CLK_SYS_TIMER RO 0x0
4 CLK_SYS_TBMAN RO 0x0
RP2040 Datasheet
2.15. Clocks 238