Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
23:12 ENABLE On power-up this field is initialised to DISABLE and the
chip runs from the ROSC.
If the chip has subsequently been programmed to run
from the XOSC then setting this field to DISABLE may
lock-up the chip. If this is a concern then run the clk_ref
from the ROSC and enable the clk_sys RESUS feature.
The 12-bit code is intended to give some protection
against accidental writes. An invalid setting will enable the
oscillator.
0xd1e → DISABLE
0xfab → ENABLE
RW -
11:0 FREQ_RANGE Frequency range. This resets to 0xAA0 and cannot be
changed.
0xaa0 → 1_15MHZ
0xaa1 → RESERVED_1
0xaa2 → RESERVED_2
0xaa3 → RESERVED_3
RW -
XOSC: STATUS Register
Offset: 0x04
Description
Crystal Oscillator Status
Table 270. STATUS
Register
Bits Name Description Type Reset
31 STABLE Oscillator is running and stable RO 0x0
30:25 Reserved. - - -
24 BADWRITE An invalid value has been written to CTRL_ENABLE or
CTRL_FREQ_RANGE or DORMANT
WC 0x0
23:13 Reserved. - - -
12 ENABLED Oscillator is enabled but not necessarily running and
stable, resets to 0
RO -
11:2 Reserved. - - -
1:0 FREQ_RANGE The current frequency range setting, always reads 0
0x0 → 1_15MHZ
0x1 → RESERVED_1
0x2 → RESERVED_2
0x3 → RESERVED_3
RO -
XOSC: DORMANT Register
Offset: 0x08
Description
Crystal Oscillator pause control
RP2040 Datasheet
2.16. Crystal Oscillator (XOSC) 243