Datasheet

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start the Crystal Oscillator (XOSC) and PLLs. The ROSC can be disabled after the system clocks have been switched to
the XOSC. Each oscillator has advantages and the programmer can switch between them to achieve the best solution
for the application.
Figure 34. ROSC
overview.
2.17.2. ROSC/XOSC trade-offs
The advantages of the ROSC are its flexibility and its low power. Also, there is no requirement for internal or external
components when using the ROSC to provide clocks. Its frequency is programmable so it can be used to provide a fast
core clock without starting the PLLs and can be divided by clock generators (Section 2.15) to generate slower peripheral
clocks. The ROSC starts immediately and responds immediately to the frequency controls. It will retain the frequency
setting when entering and exiting the DORMANT state (see Section 2.11.3). However, the user must be aware that the
frequency may have drifted when exiting the DORMANT state due to changes in the supply voltage and the chip
temperature.
The disadvantage of the ROSC is its frequency variation with PVT (Process, Voltage & Temperature) which makes it
unsuitable for generating precise clocks or for applications where software execution timing is important. However, the
PVT frequency variation can be exploited to provide automatic frequency scaling to maximise performance. This is
discussed in Section 2.15.
The only advantage of the XOSC is its accurate frequency, but this is an overriding requirement in many applications.
The disadvantages of the XOSC are its requirement for external components (a crystal etc), its higher power
consumption, slow startup time (>1ms) and fixed, low frequency. PLLs are required to produce higher frequency clocks.
They consume more power and take significant time to start up and to change frequency. Exiting DORMANT mode is
much slower than for ROSC because the XOSC must be restarted and the PLLs must be reconfigured.
2.17.3. Modifying the frequency
The ROSC is arranged as 8 stages, each with programmable drive. There are 2 methods of controlling the frequency.
The frequency range controls the number of stages in the ROSC loop and the FREQA & FREQB registers control the drive
strength of the stages.
The frequency range is changed by writing to the FREQ_RANGE register which controls the number of stages in the
ROSC loop. The default LOW range has 8 (stages 0-7), MEDIUM has 6 (stages 0-5), HIGH has 4 (stages 0-3) and
TOOHIGH has 2 (stages 0-1). It is recommended to change FREQ_RANGE one step at a time until the desired range is
reached. The ROSC output will not glitch when increasing the frequency range, so the output clock can continue to be
used. However, that is not true when going back down the frequency range. An alternate clock source must be selected
for the modules clocked by ROSC, or they must be held in reset during the transition. The behaviour has not been fully
characterised but the MEDIUM range will be approximately 1.33 times the LOW RANGE, the HIGH range will be 2 times
the LOW range and the TOOHIGH range will be 4 times the LOW range. The TOOHIGH range is aptly named. It should
not be used because the internal logic of the ROSC will not run at that frequency.
The FREQA & FREQB registers control the drive strength of the stages in the ROSC loop. Increasing the drive strength
reduces the delay through the stage and increases the oscillation frequency. Each stage has 3 drive strength control
bits. Each bit turns on additional drive, therefore each stage has 4 drive strength settings equal to the number of bits
set, with 0 being the default, 1 being double drive, 2 being triple drive and 3 being quadruple drive. Turning on extra drive
will not have a linear effect on frequency, setting a second bit will have less impact than setting the first bit and so on.
To ensure smooth transitions it is recommended to change one drive strength bit at a time. When FREQ_RANGE is used
RP2040 Datasheet
2.17. Ring Oscillator (ROSC) 245