Datasheet

Bits Name Description Type Reset
11:0 FREQ_RANGE Controls the number of delay stages in the ROSC ring
LOW uses stages 0 to 7
MEDIUM uses stages 0 to 5
HIGH uses stages 0 to 3
TOOHIGH uses stages 0 to 1 and should not be used
because its frequency exceeds design specifications
The clock output will not glitch when changing the range
up one step at a time
The clock output will glitch when changing the range
down
Note: the values here are gray coded which is why HIGH
comes before TOOHIGH
0xfa4 → LOW
0xfa5 → MEDIUM
0xfa7 → HIGH
0xfa6 → TOOHIGH
RW 0xaa0
ROSC: FREQA Register
Offset: 0x04
Description
The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
The drive strength has 4 levels determined by the number of bits set
Increasing the number of bits set increases the drive strength and increases the oscillation frequency
0 bits set is the default drive strength
1 bit set doubles the drive strength
2 bits set triples drive strength
3 bits set quadruples drive strength
Table 276. FREQA
Register
Bits Name Description Type Reset
31:16 PASSWD Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0
0x9696 → PASS
RW 0x0000
15 Reserved. - - -
14:12 DS3 Stage 3 drive strength RW 0x0
11 Reserved. - - -
10:8 DS2 Stage 2 drive strength RW 0x0
7 Reserved. - - -
6:4 DS1 Stage 1 drive strength RW 0x0
3 Reserved. - - -
2:0 DS0 Stage 0 drive strength RW 0x0
ROSC: FREQB Register
Offset: 0x08
Description
For a detailed description see freqa register
RP2040 Datasheet
2.17. Ring Oscillator (ROSC) 248