Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 13. PERFCTR3
Register
Bits Description Type Reset
31:24 Reserved. - -
23:0 Busfabric saturating performance counter 3
Count some event signal from the busfabric arbiters.
Write any value to clear. Select an event to count using PERFSEL3
WC 0x000000
BUSCTRL: PERFSEL3 Register
Offset: 0x24
Description
Bus fabric performance event select for PERFCTR3
Table 14. PERFSEL3
Register
Bits Description Type Reset
31:5 Reserved. - -
4:0 Select an event for PERFCTR3. Count either contested accesses, or all
accesses, on a downstream port of the main crossbar.
0x00 → apb_contested
0x01 → apb
0x02 → fastperi_contested
0x03 → fastperi
0x04 → sram5_contested
0x05 → sram5
0x06 → sram4_contested
0x07 → sram4
0x08 → sram3_contested
0x09 → sram3
0x0a → sram2_contested
0x0b → sram2
0x0c → sram1_contested
0x0d → sram1
0x0e → sram0_contested
0x0f → sram0
0x10 → xip_main_contested
0x11 → xip_main
0x12 → rom_contested
0x13 → rom
RW 0x1f
2.2. Address Map
The address map for the device is split in to sections as shown in Table 15. Details are shown in the following sections.
Unmapped address ranges raise a bus error when accessed.
2.2.1. Summary
Table 15. Address
Map Summary
ROM
0x00000000
XIP
0x10000000
SRAM
0x20000000
APB Peripherals
0x40000000
RP2040 Datasheet
2.2. Address Map 24