Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 277. FREQB
Register
Bits Name Description Type Reset
31:16 PASSWD Set to 0x9696 to apply the settings
Any other value in this field will set all drive strengths to 0
0x9696 → PASS
RW 0x0000
15 Reserved. - - -
14:12 DS7 Stage 7 drive strength RW 0x0
11 Reserved. - - -
10:8 DS6 Stage 6 drive strength RW 0x0
7 Reserved. - - -
6:4 DS5 Stage 5 drive strength RW 0x0
3 Reserved. - - -
2:0 DS4 Stage 4 drive strength RW 0x0
ROSC: DORMANT Register
Offset: 0x0c
Description
Ring Oscillator pause control
Table 278. DORMANT
Register
Bits Description Type Reset
31:0 This is used to save power by pausing the ROSC
On power-up this field is initialised to WAKE
An invalid write will also select WAKE
Warning: setup the irq before selecting dormant mode
0x636f6d61 → DORMANT
0x77616b65 → WAKE
RW -
ROSC: DIV Register
Offset: 0x10
Description
Controls the output divider
Table 279. DIV
Register
Bits Description Type Reset
31:12 Reserved. - -
11:0 set to 0xaa0 + div where
div = 0 divides by 32
div = 1-31 divides by div
any other value sets div=31
this register resets to div=16
0xaa0 → PASS
RW -
ROSC: PHASE Register
Offset: 0x14
Description
Controls the phase shifted output
RP2040 Datasheet
2.17. Ring Oscillator (ROSC) 249