Datasheet

Table 283. COUNT
Register
Bits Description Type Reset
31:8 Reserved. - -
7:0 A down counter running at the ROSC frequency which counts to zero and
stops.
To start the counter write a non-zero value.
Can be used for short software pauses when setting up time sensitive
hardware.
RW 0x00
2.18. PLL
2.18.1. Overview
The PLL is designed to take a reference clock, and multiply it using a VCO (Voltage Controlled Oscillator) with a
feedback loop. The VCO must run at high frequencies (between 400 and 1600 MHz), so there are two dividers, known as
post dividers that can divide the VCO frequency before it is distributed to the clock generators on the chip.
There are two PLLs in RP2040. They are:
•
pll_sys - Used to generate up to a 133 MHz system clock
•
pll_usb - Used to generate a 48 MHz USB reference clock
FREF
REFDIV
FBDIV
LOCK
FOUTVCO
CLKSSCG
Analog circuits
Post divider rate circuits
Reference rate circuits
FOUTPOSTDIV
Lock Detect
Feedback Divide
÷16-320
BYPASS
POSTDIV1 POSTDIV2
÷1-7÷1-7
PFD÷1-63
6'b 3'b 3'b
12'b
VCO
Figure 35. On both
PLLs, the FREF
(reference) input is
connected to the
crystal oscillator’s XI
input. The PLL
contains a VCO, which
is locked to a constant
ratio of the reference
clock via the feedback
loop (phase-frequency
detector and loop
filter). This can
synthesise very high
frequencies, which
may be divided down
by the post-dividers.
2.18.2. Calculating PLL parameters
To configure the PLL, you must know the frequency of the reference clock, which on RP2040 is routed directly from the
crystal oscillator. This will often be a 12 MHz crystal, for compatibility with RP2040’s USB bootrom. The PLL’s final
output frequency FOUTPOSTDIV can then be calculated as (FREF / REFDIV) × FBDIV / (POSTDIV1 × POSTDIV2). With a desired
output frequency in mind, you must select PLL parameters according to the following constraints of the PLL design:
•
Minimum reference frequency (FREF / REFDIV) is 5 MHz
•
Oscillator frequency (FOUTVCO) must be in the range 400 MHz → 1600 MHz
•
Feedback divider (FBDIV) must be in the range 16 → 320
•
The post dividers POSTDIV1 and POSTDIV2 must be in the range 1 → 7
RP2040 Datasheet
2.18. PLL 251