Datasheet

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Maximum input frequency (FREF / REFDIV) is VCO frequency divided by 16, due to minimum feedback divisor
Additionally, the maximum frequencies of the chip’s clock generators (attached to FOUTPOSTDIV) must be respected. For
the system PLL this is 133 MHz, and for the USB PLL, 48 MHz.

NOTE
The crystal oscillator on RP2040 is designed for crystals between 5 and 15 MHz, so typically REFDIV should be 1. If
the application circuit drives a faster reference directly into the XI input, and a low VCO frequency is desired, the
reference divisor can be increased to keep the PLL input within a suitable range.
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TIP
When two different values are required for POSTDIV1 and POSTDIV2, it’s preferable to assign the higher value to POSTDIV1,
for lower power consumption.
In the RP2040 reference design (see Hardware design with RP2040, Minimal Design Example), which attaches a 12 MHz
crystal to the crystal oscillator, this implies that the minimum achievable and legal VCO frequency is 12 MHz × 34 = 408
MHz, and the maximum VCO is 12 MHz × 133 = 1596 MHz, so FBDIV must remain in the range 34 → 133. For example,
setting FBDIV to 100 would synthesise a 1200 MHz VCO frequency. A POSTDIV1 value of 6 and a POSTDIV2 value of 2 would
divide this by 12 in total, producing a clean 100 MHz at the PLL’s final output.
2.18.2.1. Jitter vs Power Consumption
There are often several sets of PLL configuration parameters which achieve, or are very close to, the desired output
frequency. It is up to the programmer to decide whether to prioritise low PLL power consumption, or lower jitter, which
is cycle-to-cycle variation in the PLL’s output clock period. This is not a concern as far as system stability is concerned,
because RP2040’s digital logic is designed with margin for the worst-case possible jitter on the system clock, but a
highly accurate clock is often needed for audio and video applications, or where data is being transmitted and received
in accordance with a specification. For example, the USB specification defines a maximum amount of allowable jitter.
Jitter is minimised by running the VCO at the highest possible frequency, so that higher post-divide values can be used.
For example, 1500 MHz VCO / 6 / 2 = 125MHz. To reduce power consumption, the VCO frequency should be as low as
possible. For example: 500 MHZ VCO / 4 / 1 = 125 MHz.
Another consideration here is that slightly adjusting the output frequency may allow a much lower VCO frequency to be
achieved, by bringing the output to a closer rational multiple of the input. Indeed the exact desired frequency may not be
exactly achievable with any allowable VCO frequency, or combination of divisors.
SDK provides a Python script that searches for the best VCO and post divider options for a desired output frequency:
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/scripts/vcocalc.py Lines 1 - 37
Ê1 #!/usr/bin/env python3
Ê2
Ê3 import argparse
Ê4
Ê5 parser = argparse.ArgumentParser(description="PLL parameter calculator")
Ê6 parser.add_argument("--input", "-i", default=12, help="Input (reference) frequency. Default
Ê 12 MHz", type=float)
Ê7 parser.add_argument("--vco-max", default=1600, help="Override maximum VCO frequency. Default
Ê 1600 MHz", type=float)
Ê8 parser.add_argument("--vco-min", default=400, help="Override minimum VCO frequency. Default
Ê 400 MHz", type=float)
Ê9 parser.add_argument("--low-vco", "-l", action="store_true", help="Use a lower VCO frequency
Ê when possible. This reduces power consumption, at the cost of increased jitter")
10 parser.add_argument("output", help="Output frequency in MHz.", type=float)
11 args = parser.parse_args()
12
RP2040 Datasheet
2.18. PLL 252