Datasheet

PD2: 2
We can restrict the search to lower VCO frequencies, so that the script will consider looser frequency matches. Note
that, whilst a 500 MHz VCO would be ideal here, we can’t achieve exactly 500 MHz by multiplying the 12 MHz input by
an integer, which is why the previous invocation returned such a high VCO frequency.
$ ./vcocalc.py -l 125 --vco-max 600
Requested: 125.0 MHz
Achieved: 126.0 MHz
FBDIV: 42 (VCO = 504 MHz)
PD1: 4
PD2: 1
A 126 MHz system clock may be a tolerable deviation from the desired 125 MHz, and generating this clock consumes
less power at the PLL.
2.18.3. Configuration
The SDK uses the following PLL settings:
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_clocks/clocks.c Lines 149 - 152
149 // Configure PLLs
150 // REF FBDIV VCO POSTDIV
151 // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
152 // PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
The pll_init function in the SDK, which we will examine below, asserts that all of these conditions are true before
attempting to configure the PLL.
The SDK defines the PLL control registers as a struct. It then maps them into memory for each instance of the PLL.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2040/hardware_structs/include/hardware/structs/pll.h Lines 14 - 22
14 typedef struct {
15 io_rw_32 cs;
16 io_rw_32 pwr;
17 io_rw_32 fbdiv_int;
18 io_rw_32 prim;
19 } pll_hw_t;
20
21 #define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
22 #define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
The SDK defines pll_init which is used to configure, or reconfigure a PLL. It starts by clearing any previous power state
in the PLL, then calculates the appropriate feedback divider value. There are assertions to check these values satisfy the
constraints above.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_pll/pll.c Lines 13 - 18
13 void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
14 uint32_t ref_mhz = XOSC_MHZ / refdiv;
15
16 // What are we multiplying the reference clock by to get the vco freq
17 // (The regs are called div, because you divide the vco output and compare it to the
RP2040 Datasheet
2.18. PLL 254