Datasheet

Ê refclk)
18 uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
The programming sequence for the PLL is as follows:
•
Program the reference clock divider (is a divide by 1 in the RP2040 case)
•
Program the feedback divider
•
Turn on the main power and VCO
•
Wait for the VCO to lock (i.e. keep its output frequency stable)
•
Set up post dividers and turn them on
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_pll/pll.c Lines 41 - 70
41 if ((pll->cs & PLL_CS_LOCK_BITS) &&
42 (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
43 (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
44 (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
45 // do not disrupt PLL that is already correctly configured and operating
46 return;
47 }
48
49 uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS :
Ê RESETS_RESET_PLL_SYS_BITS;
50 reset_block(pll_reset);
51 unreset_block_wait(pll_reset);
52
53 // Load VCO-related dividers before starting VCO
54 pll->cs = refdiv;
55 pll->fbdiv_int = fbdiv;
56
57 // Turn on PLL
58 uint32_t power = PLL_PWR_PD_BITS | // Main power
59 PLL_PWR_VCOPD_BITS; // VCO Power
60
61 hw_clear_bits(&pll->pwr, power);
62
63 // Wait for PLL to lock
64 while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
65
66 // Set up post dividers
67 pll->prim = pdiv;
68
69 // Turn on post divider
70 hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
Note the VCO is turned on first, followed by the post dividers so the PLL does not output a dirty clock while the VCO is
locking.
2.18.4. List of Registers
The PLL_SYS and PLL_USB registers start at base addresses of 0x40028000 and 0x4002c000 respectively (defined as
PLL_SYS_BASE and PLL_USB_BASE in SDK).
Table 284. List of PLL
registers
Offset Name Info
0x0 CS Control and Status
RP2040 Datasheet
2.18. PLL 255