Datasheet

Offset Name Info
0x4 PWR Controls the PLL power modes.
0x8 FBDIV_INT Feedback divisor
0xc PRIM Controls the PLL post dividers for the primary output
PLL: CS Register
Offset: 0x0
Description
Control and Status
GENERAL CONSTRAINTS:
Reference clock frequency min=5MHz, max=800MHz
Feedback divider min=16, max=320
VCO frequency min=400MHz, max=1600MHz
Table 285. CS Register
Bits Name Description Type Reset
31 LOCK PLL is locked RO 0x0
30:9 Reserved. - - -
8 BYPASS Passes the reference clock to the output instead of the
divided VCO. The VCO continues to run so the user can
switch between the reference clock and the divided VCO
but the output will glitch when doing so.
RW 0x0
7:6 Reserved. - - -
5:0 REFDIV Divides the PLL input reference clock.
Behaviour is undefined for div=0.
PLL output will be unpredictable during refdiv changes,
wait for lock=1 before using it.
RW 0x01
PLL: PWR Register
Offset: 0x4
Description
Controls the PLL power modes.
Table 286. PWR
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5 VCOPD PLL VCO powerdown
To save power set high when PLL output not required or
bypass=1.
RW 0x1
4 Reserved. - - -
3 POSTDIVPD PLL post divider powerdown
To save power set high when PLL output not required or
bypass=1.
RW 0x1
2 DSMPD PLL DSM powerdown
Nothing is achieved by setting this low.
RW 0x1
1 Reserved. - - -
RP2040 Datasheet
2.18. PLL 256