Datasheet

Bits Name Description Type Reset
0 PD PLL powerdown
To save power set high when PLL output not required.
RW 0x1
PLL: FBDIV_INT Register
Offset: 0x8
Description
Feedback divisor
(note: this PLL does not support fractional division)
Table 287. FBDIV_INT
Register
Bits Description Type Reset
31:12 Reserved. - -
11:0 see ctrl reg description for constraints RW 0x000
PLL: PRIM Register
Offset: 0xc
Description
Controls the PLL post dividers for the primary output
(note: this PLL does not have a secondary output)
the primary output is driven from VCO divided by postdiv1*postdiv2
Table 288. PRIM
Register
Bits Name Description Type Reset
31:19 Reserved. - - -
18:16 POSTDIV1 divide by 1-7 RW 0x7
15 Reserved. - - -
14:12 POSTDIV2 divide by 1-7 RW 0x7
11:0 Reserved. - - -
2.19. GPIO
2.19.1. Overview
RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use
case, the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an
external flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital
input and output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC).
Each GPIO can be controlled directly by software running on the processors, or by a number of other functional blocks.
The User GPIO bank supports the following functions:
•
Software control via SIO (Single-Cycle IO) - Section 2.3.1.2, “GPIO Control”
•
Programmable IO (PIO) - Chapter 3, PIO
•
2 x SPI - Section 4.4, “SPI”
•
2 x UART - Section 4.2, “UART”
RP2040 Datasheet
2.19. GPIO 257