Datasheet

Function Name Description
CLOCK GPINx General purpose clock inputs. Can be routed to a number of internal clock domains on
RP2040, e.g. to provide a 1 Hz clock for the RTC, or can be connected to an internal
frequency counter.
CLOCK GPOUTx General purpose clock outputs. Can drive a number of internal clocks onto GPIOs, with
optional integer divide.
USB OVCUR DET/VBUS
DET/VBUS EN
USB power control signals to/from the internal USB controller
Table 291. General
Purpose Input/Output
(GPIO) QSPI Bank
Functions
Function
IO F0 F1 F2 F3 F4 F5 F6 F7 F8 F9
QSPI SCK XIP SCK SIO
QSPI CSn XIP CSn SIO
QSPI SD0 XIP SD0 SIO
QSPI SD1 XIP SD1 SIO
QSPI SD2 XIP SD2 SIO
QSPI SD3 XIP SD3 SIO
Table 292. GPIO QSPI
Bank function
descriptions
Function Name Description
XIP Connection to the synchronous serial interface (SSI) inside the flash execute in place (XIP) subsystem.
This allows processors to execute code directly from an external SPI, Dual-SPI or Quad-SPI flash
SIO
Software control of GPIO, from the single-cycle IO (SIO) block. The SIO function (F5) must be selected
for the processors to drive a GPIO, but the input is always connected, so software can check the state
of GPIOs at any time. The QSPI IOs are controlled via the SIO_GPIO_HI_x registers, and are mapped to
register bits in the order SCK, CSn, SD0, SD1, SD2, SD3, starting at the LSB.
The six QSPI Bank GPIO pins are typically used by the XIP peripheral to communicate with an external flash device.
However, there are two scenarios where the pins can be used as software-controlled GPIOs:
•
If a SPI or Dual-SPI flash device is used for execute-in-place, then the SD2 and SD3 pins are not used for flash
access, and can be used for other GPIO functions on the circuit board.
•
If RP2040 is used in a flashless configuration (USB boot only), then all six pins can be used for software-controlled
GPIO functions
2.19.3. Interrupts
An interrupt can be generated for every GPIO pin in four scenarios:
•
Level High: the GPIO pin is a logical 1
•
Level Low: the GPIO pin is a logical 0
•
Edge High: the GPIO has transitioned from a logical 0 to a logical 1
•
Edge Low: the GPIO has transitioned from a logical 1 to a logical 0
The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will
become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be
cleared by writing to the INTR register.
There are enable , status, and force registers for three interrupt destinations: proc 0, proc 1, and dormant_wake. For
RP2040 Datasheet
2.19. GPIO 260