Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x12c PROC0_INTS3 Interrupt status after masking & forcing for proc0
0x130 PROC1_INTE0 Interrupt Enable for proc1
0x134 PROC1_INTE1 Interrupt Enable for proc1
0x138 PROC1_INTE2 Interrupt Enable for proc1
0x13c PROC1_INTE3 Interrupt Enable for proc1
0x140 PROC1_INTF0 Interrupt Force for proc1
0x144 PROC1_INTF1 Interrupt Force for proc1
0x148 PROC1_INTF2 Interrupt Force for proc1
0x14c PROC1_INTF3 Interrupt Force for proc1
0x150 PROC1_INTS0 Interrupt status after masking & forcing for proc1
0x154 PROC1_INTS1 Interrupt status after masking & forcing for proc1
0x158 PROC1_INTS2 Interrupt status after masking & forcing for proc1
0x15c PROC1_INTS3 Interrupt status after masking & forcing for proc1
0x160 DORMANT_WAKE_INTE0 Interrupt Enable for dormant_wake
0x164 DORMANT_WAKE_INTE1 Interrupt Enable for dormant_wake
0x168 DORMANT_WAKE_INTE2 Interrupt Enable for dormant_wake
0x16c DORMANT_WAKE_INTE3 Interrupt Enable for dormant_wake
0x170 DORMANT_WAKE_INTF0 Interrupt Force for dormant_wake
0x174 DORMANT_WAKE_INTF1 Interrupt Force for dormant_wake
0x178 DORMANT_WAKE_INTF2 Interrupt Force for dormant_wake
0x17c DORMANT_WAKE_INTF3 Interrupt Force for dormant_wake
0x180 DORMANT_WAKE_INTS0 Interrupt status after masking & forcing for dormant_wake
0x184 DORMANT_WAKE_INTS1 Interrupt status after masking & forcing for dormant_wake
0x188 DORMANT_WAKE_INTS2 Interrupt status after masking & forcing for dormant_wake
0x18c DORMANT_WAKE_INTS3 Interrupt status after masking & forcing for dormant_wake
IO_BANK0: GPIO0_STATUS, GPIO1_STATUS, …, GPIO28_STATUS,
GPIO29_STATUS Registers
Offsets: 0x000, 0x008, …, 0x0e0, 0x0e8
Description
GPIO status
Table 294.
GPIO0_STATUS,
GPIO1_STATUS, …,
GPIO28_STATUS,
GPIO29_STATUS
Registers
Bits Name Description Type Reset
31:27 Reserved. - - -
26 IRQTOPROC interrupt to processors, after override is applied RO 0x0
25 Reserved. - - -
24 IRQFROMPAD interrupt from pad before override is applied RO 0x0
RP2040 Datasheet
2.19. GPIO 267