Datasheet

SIO_BASE
0xd0000000
Cortex-M0+ Internal Peripherals:
PPB_BASE
0xe0000000
2.3. Processor subsystem
The RP2040 processor subsystem consists of two Arm Cortex-M0+ processors — each with its standard internal Arm
CPU peripherals — alongside external peripherals for GPIO access and inter-core communication. Details of the Arm
Cortex-M0+ processors, including the specific feature configuration used on RP2040, can be found in Section 2.4.
SIO
Core 0
Cortex-M0+
Bus Interface
NVIC DAP
Core 1
Cortex-M0+
Bus Interface
NVIC DAP
To GPIO Muxing
From external debuggerFrom peripherals
GPIO ×36
To bus fabric
AHB-Lite
To bus fabric
AHB-Lite
IOPORT
Events
IOPORT
Interrupts Serial Wire Debug
Figure 6. Two Cortex-
M0+ processors, each
with a dedicated 32-bit
AHB-Lite bus port, for
code fetch, loads and
stores. The SIO is
connected to the
single-cycle IOPORT
bus of each processor,
and provides GPIO
access, two-way
communications, and
other core-local
peripherals. Both
processors can be
debugged via a single
multi-drop Serial Wire
Debug bus. 26
interrupts (plus NMI)
are routed to the NVIC
and WIC on each
processor.

NOTE
The terms core0 and core1, proc0 and proc1 are used interchangeably in RP2040’s registers and documentation to
refer to processor 0, and processor 1 respectively.
The processors use a number of interfaces to communicate with the rest of the system:
•
Each processor uses its own independent 32-bit AHB-Lite bus to access memory and memory-mapped peripherals
(more detail in Section 2.1)
•
The single-cycle IO block provides high-speed, deterministic access to GPIOs via each processor’s IOPORT
•
26 system-level interrupts are routed to both processors
•
A multi-drop Serial Wire Debug bus provides debug access to both processors from an external debug host
2.3.1. SIO
The Single-cycle IO block (SIO) contains several peripherals that require low-latency, deterministic access from the
processors. It is accessed via each processor’s IOPORT: this is an auxiliary bus port on the Cortex-M0+ which can
perform rapid 32-bit reads and writes. The SIO has a dedicated bus interface for each processor’s IOPORT, as shown in
Figure 7. Processors access their IOPORT with normal load and store instructions, directed to the special IOPORT
address segment, 0xd0000000…0xdfffffff. The SIO appears as memory-mapped hardware within the IOPORT space.
RP2040 Datasheet
2.3. Processor subsystem 27