Datasheet


NOTE
The SIO is not connected to the main system bus due to its tight timing requirements. It can only be accessed by the
processors, or by the debugger via the processor debug ports.
Core 0 Core 1
CPUID 0
CPUID 1
Integer Divider
Integer Divider
Interpolator 0
Interpolator 0
Interpolator 1
Interpolator 1
FIFO 0 to 1
FIFO 1 to 0
Bus
Interface
Hardware Spinlock ×32
GPIO Registers Shared, atomic
set/clear/xor
Bus
Interface
To GPIO Muxing
Single-cycle IO
IOPORTIOPORT
GPIO ×36
Figure 7. The single-
cycle IO block
contains memory-
mapped hardware
which the processors
must be able to
access quickly. The
FIFOs and spinlocks
support message
passing and
synchronisation
between the two
cores. The shared
GPIO registers provide
fast and concurrency-
safe direct access to
GPIO-capable pins.
Some core-local
arithmetic hardware
can be used to
accelerate common
tasks on the
processors.
All IOPORT reads and writes (and therefore all SIO accesses) take place in exactly one cycle, unlike the main AHB-Lite
system bus, where the Cortex-M0+ requires two cycles for a load or store, and may have to wait longer due to
contention from other system bus masters. This is vital for interfaces such as GPIO, which have tight timing
requirements.
SIO registers are mapped to word-aligned addresses in the range 0xd0000000…0xd000017c. The remainder of the IOPORT
space is reserved for future use.
The SIO peripherals are described in more detail in the following sections.
2.3.1.1. CPUID
The register CPUID is the first register in the IOPORT space. Core 0 reads a value of 0 when accessing this address, and
core 1 reads a value of 1. This is a convenient method for software to determine on which core it is running. This is
checked during the initial boot sequence: both cores start running simultaneously, core 1 goes into a deep sleep state,
and core 0 continues with the main boot sequence.
RP2040 Datasheet
2.3. Processor subsystem 28