Datasheet


IMPORTANT
CPUID should not be confused with the Cortex-M0+ CPUID register (Section 2.4.4.1.1) on each processor’s internal
Private Peripheral Bus, which lists the processor’s part number and version.
2.3.1.2. GPIO Control
The processors have access to GPIO registers for fast and direct control of pins with GPIO functionality. There are two
identical sets of registers:
•
GPIO_x for direct control of IO bank 0 (user GPIOs 0 to 29, starting at the LSB)
•
GPIO_HI_x for direct control of the QSPI IO bank (in the order SCLK, SSn, SD0, SD1, SD2, SD3, starting at the LSB)

NOTE
To drive a pin with the SIO’s GPIO registers, the GPIO multiplexer for this pin must first be configured to select the
SIO GPIO function. See Table 289.
These GPIO registers are shared between the two cores, and both cores can access them simultaneously. There are
three registers for each bank:
•
Output registers, GPIO_OUT and GPIO_HI_OUT, are used to set the output level of the GPIO (1/0 for high/low)
•
Output enable registers, GPIO_OE and GPIO_HI_OE, are used to enable the output driver. 0 for high-impedance, 1
for drive high/low based on GPIO_OUT and GPIO_HI_OUT.
•
Input registers, GPIO_IN and GPIO_HI_IN, allow the processor to sample the current state of the GPIOs
Reading GPIO_IN returns all 30 GPIO values (or 6 for GPIO_HI_IN) in a single read. Software can then mask out
individual pins it is interested in.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 518 - 530
518 * read using gpio_get()).
519 *
520 * To avoid races, this function must not be used for read-modify-write
521 * sequences when driving GPIOs -- instead functions like gpio_put() should be
522 * used to atomically update GPIOs. This accessor is intended for debug use
523 * only.
524 *
525 * \param gpio GPIO number
526 * \return true if the GPIO output level is high, false if low.
527 */
528 static inline bool gpio_get_out_level(uint gpio) {
529 return !!(sio_hw->gpio_out & (1u << gpio));
530 }
The OUT and OE registers also have atomic SET, CLR, and XOR aliases, which allows software to update a subset of the
pins in one operation. This is vital not only for safe parallel GPIO access between the two cores, but also safe
concurrent GPIO access in an interrupt handler and foreground code running on one core.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 452 - 454
452 static inline void gpio_set_mask(uint32_t mask) {
453 sio_hw->gpio_set = mask;
454 }
RP2040 Datasheet
2.3. Processor subsystem 29