Datasheet

SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 461 - 463
461 static inline void gpio_clr_mask(uint32_t mask) {
462 sio_hw->gpio_clr = mask;
463 }
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_gpio/include/hardware/gpio.h Lines 521 - 530
521 * sequences when driving GPIOs -- instead functions like gpio_put() should be
522 * used to atomically update GPIOs. This accessor is intended for debug use
523 * only.
524 *
525 * \param gpio GPIO number
526 * \return true if the GPIO output level is high, false if low.
527 */
528 static inline bool gpio_get_out_level(uint gpio) {
529 return !!(sio_hw->gpio_out & (1u << gpio));
530 }
If both processors write to an OUT or OE register (or any of its SET/CLR/XOR aliases) on the same clock cycle, the result
is as though core 0 wrote first, and core 1 wrote immediately afterward. For example, if core 0 SETs a bit, and core 1
simultaneously XORs it, the bit will be set to 0, irrespective of it original value.

NOTE
This is a conceptual model for the result that is produced when two cores write to a GPIO register simultaneously.
The register does not actually contain this intermediate value at any point. In the previous example, if the pin is
initially 0, and core 0 performs a SET while core 1 performs a XOR, the GPIO output remains low without any positive
glitch.
2.3.1.3. Hardware Spinlocks
The SIO provides 32 hardware spinlocks, which can be used to manage mutually-exclusive access to shared software
resources. Each spinlock is a one-bit flag, mapped to a different address (from SPINLOCK0 to SPINLOCK31). Software
interacts with each spinlock with one of the following operations:
•
Read: attempt to claim the lock. Read value is nonzero if the lock was successfully claimed, or zero if the lock had
already been claimed by a previous read.
•
Write (any value): release the lock. The next attempt to claim the lock will be successful.
If both cores try to claim the same lock on the same clock cycle, core 0 succeeds.
Generally software will acquire a lock by repeatedly polling the lock bit ("spinning" on the lock) until it is successfully
claimed. This is inefficient if the lock is held for long periods, so generally the spinlocks should be used to protect the
short critical sections of higher-level primitives such as mutexes, semaphores and queues.
For debugging purposes, the current state of all 32 spinlocks can be observed via SPINLOCK_ST.
2.3.1.4. Inter-processor FIFOs (Mailboxes)
The SIO contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
wide, and eight entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be
written by core 1, and read by core 0.
Each core writes to its outgoing FIFO by writing to FIFO_WR, and reads from its incoming FIFO by reading from FIFO_RD.
RP2040 Datasheet
2.3. Processor subsystem 30