Datasheet

Bits Name Description Type Reset
16 GPIO28_LEVEL_LOW RO 0x0
15 GPIO27_EDGE_HIGH RO 0x0
14 GPIO27_EDGE_LOW RO 0x0
13 GPIO27_LEVEL_HIGH RO 0x0
12 GPIO27_LEVEL_LOW RO 0x0
11 GPIO26_EDGE_HIGH RO 0x0
10 GPIO26_EDGE_LOW RO 0x0
9 GPIO26_LEVEL_HIGH RO 0x0
8 GPIO26_LEVEL_LOW RO 0x0
7 GPIO25_EDGE_HIGH RO 0x0
6 GPIO25_EDGE_LOW RO 0x0
5 GPIO25_LEVEL_HIGH RO 0x0
4 GPIO25_LEVEL_LOW RO 0x0
3 GPIO24_EDGE_HIGH RO 0x0
2 GPIO24_EDGE_LOW RO 0x0
1 GPIO24_LEVEL_HIGH RO 0x0
0 GPIO24_LEVEL_LOW RO 0x0
2.19.6.2. IO - QSPI Bank
The QSPI Bank IO registers start at a base address of 0x40018000 (defined as IO_QSPI_BASE in SDK).
Table 336. List of
IO_QSPI registers
Offset Name Info
0x00 GPIO_QSPI_SCLK_STATUS GPIO status
0x04 GPIO_QSPI_SCLK_CTRL GPIO control including function select and overrides.
0x08 GPIO_QSPI_SS_STATUS GPIO status
0x0c GPIO_QSPI_SS_CTRL GPIO control including function select and overrides.
0x10 GPIO_QSPI_SD0_STATUS GPIO status
0x14 GPIO_QSPI_SD0_CTRL GPIO control including function select and overrides.
0x18 GPIO_QSPI_SD1_STATUS GPIO status
0x1c GPIO_QSPI_SD1_CTRL GPIO control including function select and overrides.
0x20 GPIO_QSPI_SD2_STATUS GPIO status
0x24 GPIO_QSPI_SD2_CTRL GPIO control including function select and overrides.
0x28 GPIO_QSPI_SD3_STATUS GPIO status
0x2c GPIO_QSPI_SD3_CTRL GPIO control including function select and overrides.
0x30 INTR Raw Interrupts
0x34 PROC0_INTE Interrupt Enable for proc0
RP2040 Datasheet
2.19. GPIO 309